Conventional digital-to-analog converters (“DACs”) are typically provided with an output amplifier for buffering the DAC output. Output amplifiers are often configured as unity gain buffers, which transmit information in response to changes in potential (e.g., voltage, electromotive force) applied to their non-inverting node. A common limitation in such output buffer configurations is the bandwidth capability (e.g., the rate at which a DAC may switch from one code to another) of the output amplifier. In addition to bandwidth limitations, these output buffer configurations are also prone to non-linearities that arise from common-mode voltage changes seen by the amplifier input stage such as changes in potential applied to the non-inverting node of the output amplifier.
Prior attempts to avoid these problems have focused on reducing the sensitivity of the input stage to changes in the common-mode voltage. For circuits configured to operate using only a single supply, however, this approach of reducing the sensitivity of the input stage necessitates that the input stage be configured to accommodate the shift in potential, varying from a positive reference potential to a ground potential, applied to the non-inverting node of the output amplifier. As a result, these output amplifiers have been required to employ P-type (e.g., PMOS, PNP) input stages. Unfortunately, however, such architectures are prone to problems, such as performance degradation and reduced speed relative to more desirable N-type (e.g., NPN, NMOS) input stages. Reduced speed, in turn, reduces the bandwidth capability of these DAC circuits.
For example, with reference to FIG. 1, a schematic diagram of a prior art DAC 100 is illustrated. DAC 100 includes a switched DAC circuit 104 and an output amplifier 108. DAC circuit 104 is configured in an R-2R ladder arrangement and comprises a plurality of sampling branches with DAC sampling switches 110. DAC switches 110 are configured to switch between a low reference source 112 and a high reference source 114. Output amplifier 108 comprises an operational amplifier configured as a voltage follower, with the output of amplifier 108 configured in a feedback arrangement with the inverting input terminal. An output 102 of switched DAC circuit 104 is coupled to a non-inverting input terminal 106 of output amplifier 108.
In response to the activation of one or more DAC switches 110, the potential of high reference source 114 is enabled to generate a code-dependent voltage 102, which is applied to the non-inverting terminal 106 of output buffer 108. It should be noted that the change in code dependent voltage 102 causes changes in current 116, which flows through switches 110 or any other sampling branch connected to code dependent voltage 102. DAC switches 110, which may be implemented as MOSFET semiconductors, may introduce non-linearities due to changes in current 116. While an ideal switch theoretically exhibits a constant low resistance independent of current, in reality, variations in current through the switches of a DAC may cause potential linearity errors in the output of the DAC. As a result, voltage 102 may not exhibit steady performance, but instead, may exhibit slight errors or non-linearities in response to switching from low reference source 112 to high reference source 114.
With reference to FIG. 2, a schematic diagram of another prior art circuit 200 is illustrated, wherein the gain of an output amplifier 208 may be modified by coupling resistors 224 and 284 to an output 202 and inverting node 220 of amplifier 208. It should be noted that if amplifiers 108, 208 depicted in the circuits of FIGS. 1 and 2 are to be operated using only a single positive supply (e.g., reference potential 114 is positive), and if low reference source 112 is at ground potential (e.g., the potential of the amplifier's non-inverting node must swing to ground), then the input stages of amplifiers 108, 208 will be required to be configured as PMOS input stages, thus realizing bandwidth limitations.
Accordingly, a need exists for improved DACs wherein the bandwidth and linearity can be increased.